Integrated circuits, and particularly semiconductor memory devices utilize capacitors in a variety of ways. Dynamic random access memory devices (DRAMs) in particular employ capacitors to store charge representing a data bit. As the minimum feature size and cell architecture are scaled down, robust design points for DRAM cells utilizing planar metal oxide semiconductor field effect transistors (MOSFETs) and deep trench (DT) capacitors are increasingly difficult to achieve.
The vertical MOSFET device provides a means for better DRAM scaling, since the channel length of a vertical MOSFET is decoupled from, and is independent of, the minimum lithographic feature size used elsewhere on the chip, thus not impacting the overall device density on the chip.
FIG. 1 illustrates a conventional DRAM cell 1 that contains a vertical MOSFET 2 coupled with a DT capacitor 4. Specifically, the entire DRAM cell 1 is located in a trench formed in a semiconductor substrate 10.
The DT capacitor 4 is located in a lower portion of the trench and comprises a buried plate electrode (or outer electrode) 42, a node dielectric layer 44, and a conductive trench fill (or inner electrode) 46. The outer electrode 42 is typically formed by doping the sidewalls of the lower portion of the trench with an n-type or a p-type dopant species, and the inner electrode 46 typically comprises polysilicon doped with the same n-type or p-type dopant species as the outer electrode 42.
The vertical MOSFET 2 is located on top of the DT capacitor 4 in an upper portion of the trench. The vertical MOSFET 2 comprises a bit contact diffusion (or source) region 22, a buried strap out-diffusion (or drain) region 24, a channel region 23 located between 22 and 24, a gate dielectric layer 28, and a gate electrode 26. The channel region 23 of the vertical MOSFET 2 is electrically isolated from the gate electrode 26 by the gate dielectric layer 28.
The drain region 24 of the vertical MOSFET 2 is electrically connected with the inner electrode 46 of the DT capacitor 4. However, the gate electrode 26 of the vertical MOSFET 2 is electrically isolated from the inner electrode 46 of the DT capacitor 4 by a horizontal isolation layer 32, and the drain region 24 of the vertical MOSFET 2 is electrically isolated from the outer electrode 42 of the DT capacitor 4 by a vertical isolation collar 34 that is formed over the trench sidewalls. A pad layer 16 covers a surface of the semiconductor substrate 10 around the trench. A conductive plug 12 formed of either doped polysilicon or any other suitable conductive material is provided at the trench opening as the gate contact for the vertical MOSFET 2. An optional sidewall spacer 14 can further be provided to ensure complete electrical isolation between the conductive plug 12 and the source region 22 of the vertical MOSFET 2.
There is a continuing need for improved vertical MOSFET structures that can be readily incorporated into the DRAM devices to improve the device performance.
There is further a need for methods that can readily integrate the processing steps required for fabricating such improved vertical MOSFET structures into the DRAM device fabrication processes.